//listing of all techniques and passes with embedded asm listings 

technique FogTechnique
{
    pass p1
    {
        vertexshader = 
            asm {
            
//
            // Generated by Microsoft (R) D3DX9 Shader Compiler 9.12.589.0000
            //
            // Parameters:
            //
            //   float4x4 C0;
            //   float4x4 C20;
            //   float4 C41;
            //   float4 C50;
            //   float4 C55;
            //   float4 C59;
            //   float4 C60;
            //   float4 C61;
            //   float4 C62;
            //   float4 C63;
            //   float4 C64;
            //   float4 C65;
            //   float4 C66;
            //   float4x4 C8;
            //
            //
            // Registers:
            //
            //   Name         Reg   Size
            //   ------------ ----- ----
            //   C0           c0       4
            //   C41          c4       1
            //   C50          c5       1
            //   C8           c8       4
            //   C20          c20      4
            //   C55          c55      1
            //   C59          c59      1
            //   C60          c60      1
            //   C61          c61      1
            //   C62          c62      1
            //   C63          c63      1
            //   C64          c64      1
            //   C65          c65      1
            //   C66          c66      1
            //
            
                vs_1_1
                def c6, 0, 1, 0, 0
                dcl_position v0
                mul r0, v0.y, c9
                mad r0, c8, v0.x, r0
                mad r0, c10, v0.z, r0
                mul r1, v0.y, c1
                add r0, r0, c11
                mad r2, c0, v0.x, r1
                add r1, -r0, c5
                mad r2, c2, v0.z, r2
                dp4 r1.w, r1, r1
                add oPos, r2, c3
                rsq r2.w, r1.w
                mul r1.w, r0.y, c21.z
                mul r1.xyz, r1, r2.w
                mad r1.w, c20.z, r0.x, r1.w
                dp3 r2.x, c4, r1
                mad r1.w, c22.z, r0.z, r1.w
                min r2.w, r2.x, c6.x
                mad r0.w, c23.z, r0.w, r1.w
                mad r1.w, c63.z, r2.w, c63.y
                mul r0.w, r0.w, c66.x
                rsq r1.w, r1.w
                mul r2.xyz, -r0.w, c61
                mul r0.w, r1.w, r1.w
                mul r2.xyz, r2, c64.y
                mul r0.w, r1.w, r0.w
                exp r3.x, r2.x
                exp r3.y, r2.y
                exp r3.z, r2.z
                mul r1.w, r0.w, c63.x
                mad r0.w, r2.w, r2.w, c6.y
                mul r2.xyz, r1.w, c60
                add r3.xyz, -r3, c64.x
                mad r2.xyz, c59, r0.w, r2
                mov oT1.xyz, r0
                mul r0.xyz, r3, r2
                mov oT4.xyz, r1
                mul r0.xyz, r0, c62
                mul oT0.xyz, r0, c65.y
                mov oT0.w, c6.x
                mov oT2.xyz, c4
                mov oT3, c55
            
            // approximately 68 instruction slots used
            
}; pixelshader = asm {
//
            // Generated by Microsoft (R) D3DX9 Shader Compiler 9.12.589.0000
            //
            // Parameters:
            //
            //   float4 C41;
            //
            //
            // Registers:
            //
            //   Name         Reg   Size
            //   ------------ ----- ----
            //   C41          c0       1
            //
            
                preshader
                mov r0.x, c0.x
                mov r0.z, c0.z
                mov r0.y, (0)
                dot r1.w, r0.xyz, r0.xyz
                rsq r0.w, r1.w
                mul c4.x, r0.w, c0.x
                mul c4.y, r0.w, c0.z
                mov c5.x, (1)
            
            // approximately 8 instructions used
            //
            // Generated by Microsoft (R) D3DX9 Shader Compiler 9.12.589.0000
            //
            // Parameters:
            //
            //   float4 C41;
            //   float4 C50;
            //
            //
            // Registers:
            //
            //   Name         Reg   Size
            //   ------------ ----- ----
            //   C41          c6       1
            //   C50          c7       1
            //
            
                ps_2_0
                def c0, 1, 0, 512, 0.949999988
                def c1, 1.20000005, 1.08000004, 0.899999976, 0
                def c2, 0.699999988, 0.899999976, 0, 0
                def c3, 0.300000012, 0.600000024, 0, 0
                dcl t1.xyz
                add r1.xyz, -t1, c7
                mov r0.w, c0.y
                nrm r0.xyz, r1
                mul r1.w, r0.x, r0.x
                mad r0.w, r0.w, r0.w, r1.w
                mad r0.w, r0.z, r0.z, r0.w
                rsq r0.w, r0.w
                mul r1.xz, r0, r0.w
                mov r1.y, c0.y
                mov r2.x, -c4.x
                mov r2.z, -c4.y
                mov r2.y, c0.y
                dp3 r1.x, r1, r2
                mul r0.w, r1.x, r1.x
                dp3 r0.x, c6, -r0
                abs r1.w, r0.y
                max r3.w, r0.x, c0.y
                pow r2.w, r3.w, c0.z
                add r3.w, -r1.w, c0.x
                mul r1.w, r3.w, r3.w
                mad r3.w, r3.w, -r3.w, c0.x
                mul r0.xy, r1.w, c2
                add r1.w, -r2.w, c0.w
                mad r1.xy, r3.w, c3, r0
                cmp r2.w, r1.w, r2.w, c0.x
                max_sat r0.xy, r1, c0.y
                add r1.w, -r2.w, c0.x
                mov r0.z, c5.x
                mul r0.w, r0.w, r2.w
                mul r0.xyz, r0, r1.w
                mad_sat r0.xyz, r0.w, c1, r0
                mov r0.w, c0.x
                mov oC0, r0
            
            // approximately 37 instruction slots used
            
}; } }